Rtl Development Jobs In Hong Kong - 7 Job Positions Available

Duties Perform RTL to GDSII design flow, including floor planning, power grid design, place and route, clock tree synthesis, timing closure, power/signal integrity signoff, EM/IR. Perform full‑chip DRC/LVS. Automate the design flow to promote efficiency, improve RTL to

Join to apply for the FPGA Design - Principal Engineer / Lead Engineer / Senior Engineer / Engineer role at ASTRI - Hong Kong Applied Science and Technology Research Institute 2 weeks ago Be among the

Responsibilities Microarchitecture and design in Verilog/System Verilog. Define and own ASIC design methodologies. Integrate complex IPs developed by internal groups as well as other vendors. Block and chip level RTL verification and gate-level netlist testing. Support other