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Work on advanced DevSecOps and automation initiatives Drive AI‑enabled security enhancements across pipelines About Our Client Our client is a large organization within the Technology & Telecoms sector. The company is focused on delivering innovative solutions
Responsibilities Microarchitecture and design in Verilog/System Verilog. Define and own ASIC design methodologies. Integrate complex IPs developed by internal groups as well as other vendors. Block and chip level RTL verification and gate-level netlist testing. Support
