Hong Kong Applied Science and Technology Research Institute (ASTRI) invites qualified professionals to join our team in HK. You will work on physical layer FPGA solutions for 5G/6G R&D projects, delivering high‑performance wireless FPGA implementations and
Hong Kong Applied Science and Technology Research Institute (ASTRI) is founded in 2000 by the Government of the Hong Kong Special Administrative Region. As Hong Kong’s largest government-funded research and development centre, ASTRI is a key force
Duties Perform RTL to GDSII design flow, including floor planning, power grid design, place and route, clock tree synthesis, timing closure, power/signal integrity signoff, EM/IR. Perform full‑chip DRC/LVS. Automate the design flow to promote efficiency, improve RTL to
Responsibilities Microarchitecture and design in Verilog/System Verilog. Define and own ASIC design methodologies. Integrate complex IPs developed by internal groups as well as other vendors. Block and chip level RTL verification and gate-level netlist testing. Support other
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