Duties Perform RTL to GDSII design flow, including floor planning, power grid design, place and route, clock tree synthesis, timing closure, power/signal integrity signoff, EM/IR. Perform full‑chip DRC/LVS. Automate the design flow to promote efficiency, improve RTL to
Pinpoint Asia is partnering with a leading global quantitative investment group. Known for their scientific approach to investing and collaborative culture, they operate across all asset classes worldwide. They are currently entering a significant growth phase,
Responsibilities Microarchitecture and design in Verilog/System Verilog. Define and own ASIC design methodologies. Integrate complex IPs developed by internal groups as well as other vendors. Block and chip level RTL verification and gate-level netlist testing. Support other
A Senior UI Designer with exceptional aesthetic sense and international vision. Responsible for the overall visual system of overseas stablecoin payment apps and card business platforms. The core of payment products is trust. The mission is
Hong Kong Applied Science and Technology Research Institute (ASTRI) is founded in 2000 by the Government of the Hong Kong Special Administrative Region. As Hong Kong’s largest government-funded research and development centre, ASTRI is a key force
At OKX, we believe that the future will be reshaped by crypto, and ultimately contribute to every individuals freedom. OKX is a leading crypto exchange, and the developer of OKX Wallet, giving millions access to crypto
Join to apply for the FPGA Design - Principal Engineer / Lead Engineer / Senior Engineer / Engineer role at ASTRI - Hong Kong Applied Science and Technology Research Institute 2 weeks ago Be among the
Binance is a leading global blockchain ecosystem behind the world’s largest cryptocurrency exchange by trading volume and registered users. We are trusted by 300+ million people in 100+ countries for our industry-leading security, user fund transparency,