Responsibilities Implement basicDFT schemes, including scan insertion, boundary scan, Mem BIST, DRC Clean, ATPG and pattern simulation Support ATE bring-up, and debug the ATE patterns for production flow Support logic BIST and Memory BIST diagnosis for
Credo is looking for a candidate in Hong Kong to implement DFT schemes like scan insertion and boundary scan. Responsibilities also include pattern simulation and supporting ATE bring-up. The ideal candidate should have a Master’s degree in
Duties Perform RTL to GDSII design flow, including floor planning, power grid design, place and route, clock tree synthesis, timing closure, power/signal integrity signoff, EM/IR. Perform full‑chip DRC/LVS. Automate the design flow to promote efficiency, improve
Responsibilities Microarchitecture and design in Verilog/System Verilog. Define and own ASIC design methodologies. Integrate complex IPs developed by internal groups as well as other vendors. Block and chip level RTL verification and gate-level netlist testing. Support
Responsible for hardware development of home appliances and kitchen appliance products. Lead and be responsible for technical evaluations of projects, drafting project scope, transforming and organizing requirements specifications, planning, development, and validation. Responsible for the complete
We build consumer devices to interface with and command AI agents. Our products treat hardware as an interface and control surface, not an end in itself. We design and sell products for the global market, starting
